BIDIROE=0, SPMIE=0, RXDMAE=0, SPC0=0, MODFEN=0, SPISWAI=0, TXDMAE=0
SPI control register 2
SPC0 | SPI pin control 0 0 (0): SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in. 1 (1): SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI. |
SPISWAI | SPI stop in wait mode 0 (0): SPI clocks continue to operate in wait mode 1 (1): SPI clocks stop when the MCU enters wait mode |
RXDMAE | Receive DMA enable 0 (0): DMA request for receive is disabled and interrupt from SPRF is allowed 1 (1): DMA request for receive is enabled and interrupt from SPRF is disabled |
BIDIROE | Bidirectional mode output enable 0 (0): Output driver disabled so SPI data I/O pin acts as an input 1 (1): SPI I/O pin enabled as an output |
MODFEN | Master mode-fault function enable 0 (0): Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI 1 (1): Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output |
TXDMAE | Transmit DMA enable 0 (0): DMA request for transmit is disabled and interrupt from SPTEF is allowed 1 (1): DMA request for transmit is enabled and interrupt from SPTEF is disabled |
SPMIE | SPI match interrupt enable 0 (0): Interrupts from SPMF inhibited (use polling) 1 (1): When SPMF is 1, requests a hardware interrupt |